Integrated circuits are typically formed on a semiconductor substrate such as a silicon wafer or other semiconducting material. In general, layers of various materials which are either semiconducting, conducting or insulating are utilized to form the integrated circuits. By way of example, the various materials are doped, ion implanted, deposited, etched, grown, etc. using various processes. A continuing goal in semiconductor processing is to continue to strive to reduce the size of individual electronic components thereby enabling smaller and denser integrated circuitry.
One technique for patterning and processing semiconductor substrates is photolithography. Such typically includes deposition of a patternable masking layer commonly known as photoresist. Such materials can be processed to modify their solubility in certain solvents, and are thereby readily usable to form patterns on a substrate. For example, portions of a deposited photoresist layer can be exposed to actinic energy through openings in a mask or reticle to change the solvent solubility of the exposed regions versus the unexposed regions compared to the solubility in the as-deposited state. Thereafter, the exposed or unexposed regions can be removed, depending on the type of photoresist, thereby leaving a masking pattern of the photoresist on the substrate. Adjacent areas of the underlying substrate next to the masked portions can be processed, for example by etching or ion implanting, to effect the desired processing of the substrate adjacent the masking material. In certain instances, multiple different layers of photoresists and/or a combination of photoresists with non-radiation sensitive masking materials are utilized.
Regardless, it is important in photolithographic processing that the various masks or reticles utilized be very precisely aligned relative to the substrate being processed. This is typically conducted in part by forming some sort of alignment registration markings on the substrate being processed. Accordingly, the mask or reticle is precisely aligned relative to such markings on the substrate immediately prior to processing the resist layer utilizing the mask or reticle.
The alignment registration marks are typically fabricated on areas of the substrate which will not be utilized for fabricating operable circuitry. In one example, a series of such marks are patterned about a peripheral-most region of the substrate being processed. Alternately by way of example only, the alignment registration markings might be fabricated in street or scribeline area between individual die. Regardless, the alignment registration markings are typically several regions of a plurality of parallel trenches which are formed within the substrate. These markings are also typically fabricated commensurate with fabricating operable circuitry elsewhere on the substrate.
In DRAM circuitry fabrication, one exemplary place where these alignment marks are fabricated is commensurate with deep, narrow contact openings which are fabricated through one or more dielectric layers to ultimately make electrical connection with bit lines, word lines, or other conductive regions underlying the insulative material. In present generation processing, these contact openings might be only 0.15 micron wide, and of roughly the same length. Alignment registration markings are typically quite larger, for example, with individual trenches having an exemplary width of 1.2 microns and an exemplary length of 20 microns.
The contact openings are ultimately filled with some suitable conductive material, for example tungsten with or without conductive barrier layer materials. The conductive material is deposited to a thickness sufficiently thick to fill the contact openings but insufficiently thick to fill the alignment registration markings. Accordingly, such markings are typically lined with the conductive material and not completely filled therewith.
The typical manner by which the excess conductive material is removed to form isolated conductive contacts within the contact openings is by chemical mechanical polishing. Such utilizes a slurry having liquid and solid components which is polished against the outer substrate surface using a rotating pad. The conductive material is accordingly chemically and mechanically abraded away from the outer surface at least to the insulative material therebeneath, thereby forming isolated conductive contacts to circuitry regions beneath the insulative layer.
A continuing challenge with chemical mechanical polishing is cleaning of the substrate subsequent to the polishing. In the above-described environment, a solid particulate slurry material can become lodged within the alignment registration markings and can be difficult to remove. Various cleaning techniques have been developed, with most including utilizing cleaning solutions with or without soft brush scrubbing of the outer polished surface. Yet it has been found in the above-described environment, particulate contamination can still be problematic utilizing conventional cleaning techniques such as brush cleaning, or with independent immersion or plasma cleaning techniques.
While the invention was principally motivated in addressing the above issues, it is in no way so limited. The invention is only limited by the accompanying claims as literally worded, without interpretative or other limiting reference to the specification, and in accordance with the doctrine of equivalents.